Lines Matching refs:dev
31 void E1000_Configure(PCIDevice dev);
131 PCIDevice dev;
170 PCIDevice dev;
172 dev.bus = bus;
173 dev.slot = slot;
174 dev.func = func;
175 dev.vendor = PCI_GetVendorID(&dev);
176 dev.device = PCI_GetDeviceID(&dev);
178 uint32_t device = dev.vendor << 16 | dev.device;
185 E1000_Configure(dev);
193 MMIO_Read32(E1000Dev *dev, uint64_t addr)
195 return *(uint32_t volatile *)(dev->mmiobase + addr);
199 MMIO_Write32(E1000Dev *dev, uint64_t addr, uint32_t val)
201 *(uint32_t *)(dev->mmiobase + addr) = val;
205 E1000_EEPROM_Read(E1000Dev *dev, uint8_t addr)
210 MMIO_Write32(dev, E1000_REG_EERD, ((uint32_t)addr << 8) | 1);
214 val = MMIO_Read32(dev, E1000_REG_EERD);
225 E1000_TXPoll(E1000Dev *dev)
232 E1000_RXPoll(E1000Dev *dev)
234 while (dev->rxDesc[dev->rxTail].status & RDESC_STATUS_DD) {
235 //void *data = (void *)DMPA2VA(dev->rxDesc[dev->rxTail].addr);
236 //uint16_t len = dev->rxDesc[dev->rxTail].len;
239 if ((dev->rxDesc[dev->rxTail].status & RDESC_STATUS_EOP) &&
240 (dev->rxDesc[dev->rxTail].errors == 0)) {
248 Semaphore_Release(&dev->ioSema);
251 if (dev->rxDesc[dev->rxTail].errors) {
253 dev->rxDesc[dev->rxTail].errors);
254 dev->rxDesc[dev->rxTail].status = 0;
255 dev->rxDesc[dev->rxTail].errors = 0;
256 MMIO_Write32(dev, E1000_REG_RDT, dev->rxTail);
257 dev->rxTail = (dev->rxTail + 1) % E1000_RX_QLEN;
261 dev->rxDesc[dev->rxTail].status = 0;
262 dev->rxDesc[dev->rxTail].errors = 0;
264 MMIO_Write32(dev, E1000_REG_RDT, dev->rxTail);
265 dev->rxTail = (dev->rxTail + 1) % E1000_RX_QLEN;
273 E1000Dev *dev = (E1000Dev *)arg;
276 dev->dev.bus, dev->dev.slot);
278 uint32_t cause = MMIO_Read32(dev, E1000_REG_ICR);
283 MMIO_Write32(dev, E1000_REG_CTRL, MMIO_Read32(dev, E1000_REG_CTRL) | CTRL_SLU);
289 E1000_TXPoll(dev);
295 kprintf("underrun %u %u\n", MMIO_Read32(dev, E1000_REG_RDH), dev->rxTail);
297 E1000_RXPoll(dev);
303 E1000_RXPoll(dev);
310 MMIO_Read32(dev, E1000_REG_ICR);
319 E1000Dev *dev = (E1000Dev *)nic;
322 Semaphore_Acquire(&dev->ioSema);
324 Spinlock_Lock(&dev->lock);
325 if ((dev->rxDesc[dev->rxTail].status & RDESC_STATUS_EOP) &&
326 (dev->rxDesc[dev->rxTail].errors == 0)) {
327 void *data = (void *)DMPA2VA(dev->rxDesc[dev->rxTail].addr);
328 uint16_t len = dev->rxDesc[dev->rxTail].len;
334 dev->rxDesc[dev->rxTail].status = 0;
335 dev->rxDesc[dev->rxTail].errors = 0;
337 MMIO_Write32(dev, E1000_REG_RDT, dev->rxTail);
338 dev->rxTail = (dev->rxTail + 1) % E1000_RX_QLEN;
345 dev->rxTail,
346 dev->rxDesc[dev->rxTail].status,
347 dev->rxDesc[dev->rxTail].errors);*/
348 Spinlock_Unlock(&dev->lock);
351 Spinlock_Unlock(&dev->lock);
362 E1000Dev *dev = (E1000Dev *)nic;
363 void *data = (void *)DMPA2VA(dev->txDesc[dev->txTail].addr);
367 dev->txDesc[dev->txTail].len = mbuf->len;
369 dev->txDesc[dev->txTail].cmd = TDESC_CMD_EOP | TDESC_CMD_IFCS | TDESC_CMD_RS;
370 MMIO_Write32(dev, E1000_REG_TDT, dev->txTail);
371 dev->txTail = (dev->txTail + 1) % E1000_TX_QLEN;
379 E1000_RXInit(E1000Dev *dev)
385 MMIO_Write32(dev, E1000_REG_MTABASE + (i * 4), 0);
388 dev->rxDesc = (E1000RXDesc *)E1000RXDesc_Alloc();
390 dev->rxDesc[i].addr = VA2PA((uintptr_t)PAlloc_AllocPage()); // LOOKUP IN PMAP
391 dev->rxDesc[i].status = 0;
395 uintptr_t base = VA2PA((uintptr_t)dev->rxDesc);
396 MMIO_Write32(dev, E1000_REG_RDBAH, (uint32_t)(base >> 32));
397 MMIO_Write32(dev, E1000_REG_RDBAL, (uint32_t)(base & 0xFFFFFFFF));
398 MMIO_Write32(dev, E1000_REG_RDLEN, E1000_RX_QLEN * 16);
400 MMIO_Write32(dev, E1000_REG_RDH, 0);
401 MMIO_Write32(dev, E1000_REG_RDT, E1000_RX_QLEN);
402 dev->rxTail = 0;
404 MMIO_Write32(dev, E1000_REG_RCTL,
409 E1000_TXInit(E1000Dev *dev)
413 dev->txDesc = (E1000TXDesc *)E1000RXDesc_Alloc();
415 dev->txDesc[i].addr = VA2PA((uintptr_t)PAlloc_AllocPage()); // LOOKUP IN PMAP
416 dev->txDesc[i].cmd = 0;
420 uintptr_t base = VA2PA((uintptr_t)dev->txDesc);
421 MMIO_Write32(dev, E1000_REG_TDBAH, (uint32_t)(base >> 32));
422 MMIO_Write32(dev, E1000_REG_TDBAL, (uint32_t)(base & 0xFFFFFFFF));
423 MMIO_Write32(dev, E1000_REG_TDLEN, E1000_TX_QLEN * 16);
425 MMIO_Write32(dev, E1000_REG_TDH, 0);
426 MMIO_Write32(dev, E1000_REG_TDT, 0);
427 dev->txTail = 0;
430 MMIO_Write32(dev, E1000_REG_TIDV, 1);
431 MMIO_Write32(dev, E1000_REG_TADV, 1);
433 MMIO_Write32(dev, E1000_REG_TCTL, TCTL_EN | TCTL_PSP);
437 E1000_Configure(PCIDevice dev)
440 PCI_Configure(&dev);
455 memcpy(ðDev->dev, &dev, sizeof(dev));
460 if (dev.bars[bar].size == 0)
464 bar, dev.bars[bar].base, dev.bars[bar].size,
465 dev.bars[bar].type == PCIBAR_TYPE_IO ? "IO" : "Mem");
468 ethDev->mmiobase = (uint8_t *)DMPA2VA(dev.bars[0].base);
474 kprintf("E1000: IRQ %d\n", dev.irq);
475 ethDev->irqHandle.irq = dev.irq;
478 IRQ_Register(dev.irq, ðDev->irqHandle);