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| #define | PGNUMMASK 0xFFFFFFFFFFFFF000ULL |
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| #define | PGIDXSHIFT 9 |
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| #define | PGIDXMASK (512 - 1) |
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| #define | PGSHIFT 12 |
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| #define | PGSIZE (1 << PGSHIFT) |
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| #define | PGMASK (PGSIZE - 1) |
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| #define | LARGE_PGSHIFT 21 |
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| #define | LARGE_PGSIZE (1 << LARGE_PGSHIFT) |
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| #define | LARGE_PGMASK (LARGE_PGSIZE - 1) |
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| #define | HUGE_PGSHIFT 30 |
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| #define | HUGE_PGSIZE (1 << HUGE_PGSHIFT) |
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| #define | HUGE_PGMASK (HUGE_PGSIZE - 1) |
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| #define | ROUNDUP_PGSIZE(x) (((x) + LARGE_PGSIZE - 1) & ~LARGE_PGMASK) |
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| #define | ROUNDDOWN_PGSIZE(x) ((x) & ~LARGE_PGMASK) |
| |
| #define | PTE_P 0x0001 /* Present */ |
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| #define | PTE_W 0x0002 /* Writeable */ |
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| #define | PTE_U 0x0004 /* User */ |
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| #define | PTE_PWT 0x0008 /* Write Through */ |
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| #define | PTE_PCD 0x0010 /* Cache Disable */ |
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| #define | PTE_A 0x0020 /* Accessed */ |
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| #define | PTE_D 0x0040 /* Dirty */ |
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| #define | PTE_PS 0x0080 /* Page Size */ |
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| #define | PTE_G 0x0100 /* Global */ |
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| #define | PTE_OS1 0x0200 /* Available */ |
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| #define | PTE_OS2 0x0400 /* Available */ |
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| #define | PTE_OS3 0x0800 /* Available */ |
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| #define | PTE_PAT 0x1000 /* Page Attribute Table */ |
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| #define | PTE_NX 0x8000000000000000ULL /* No Execute */ |
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| #define | PAGETABLE_ENTRIES 512 |
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| #define | SEG_G |
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| #define | SEG_DB |
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| #define | SEG_L |
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| #define | SEG_P |
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| #define | SEG_DPL_SHIFT 45 |
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| #define | SEG_S |
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| #define | SEG_CS (0xE << 40) |
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| #define | SEG_DS (0x2 << 40) |
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| #define | SEG_TSA (0x9 << 40) |
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| #define | SEG_TSB (0xB << 40) |
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| #define | SEL_KCS 0x08 |
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| #define | SEL_KDS 0x10 |
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| #define | SEL_TSS 0x20 |
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| #define | SEL_UCS 0x30 |
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| #define | SEL_UDS 0x38 |
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| #define | CR0_PE 0x00000001 /* Protection Enabled */ |
| |
| #define | CR0_MP 0x00000002 /* Monitor Coprocessor */ |
| |
| #define | CR0_EM 0x00000004 /* Emulation */ |
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| #define | CR0_TS 0x00000008 /* Task Switched */ |
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| #define | CR0_ET 0x00000010 /* Extension Type */ |
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| #define | CR0_NE 0x00000020 /* Numeric Error */ |
| |
| #define | CR0_WP 0x00010000 /* Write Protect */ |
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| #define | CR0_AM 0x00040000 /* Alignment Mask */ |
| |
| #define | CR0_NW 0x20000000 /* Not Writethrough */ |
| |
| #define | CR0_CD 0x40000000 /* Cache Disable */ |
| |
| #define | CR0_PG 0x80000000 /* Paging */ |
| |
| #define | CR4_VME 0x00000001 /* Virtual 8086 Mode Enable */ |
| |
| #define | CR4_PVI 0x00000002 /* Protected-Mode Virtual Interupts */ |
| |
| #define | CR4_TSD 0x00000004 /* Time Stamp Diable */ |
| |
| #define | CR4_DE 0x00000008 /* Debugging Extensions */ |
| |
| #define | CR4_PSE 0x00000010 /* Page Size Extensions */ |
| |
| #define | CR4_PAE 0x00000020 /* Physical Address Extension */ |
| |
| #define | CR4_MCE 0x00000040 /* Machine Check Enable */ |
| |
| #define | CR4_PGE 0x00000080 /* Page Global Enable */ |
| |
| #define | CR4_PCE 0x00000100 /* Performance Monitoring Counter Enable */ |
| |
| #define | CR4_OSFXSR 0x00000200 /* OS FXSAVE/FXRSTOR Support */ |
| |
| #define | CR4_OSXMMEXCPT 0x00000400 /* OS Unmasked Exception Support */ |
| |
| #define | CR4_FSGSBASE 0x00010000 /* Enable FS/GS read/write Instructions */ |
| |
| #define | CR4_OSXSAVE 0x00040000 /* XSAVE and Processor Extended States Enable */ |
| |
| #define | RFLAGS_CF 0x00000001 /* Carry Flag */ |
| |
| #define | RFLAGS_PF 0x00000004 /* Parity Flag */ |
| |
| #define | RFLAGS_AF 0x00000010 /* Adjust Flag */ |
| |
| #define | RFLAGS_ZF 0x00000040 /* Zero Flag */ |
| |
| #define | RFLAGS_SF 0x00000080 /* Sign Flag */ |
| |
| #define | RFLAGS_TF 0x00000100 /* Trap Flag */ |
| |
| #define | RFLAGS_IF 0x00000200 /* Interrupt Enable Flag */ |
| |
| #define | RFLAGS_DF 0x00000400 /* Direction Flag */ |
| |
| #define | RFLAGS_OF 0x00000800 /* Overflow Flag */ |
| |
| #define | RFLAGS_NT 0x00004000 /* Nested Task Flag */ |
| |
| #define | RFLAGS_RF 0x00010000 /* Resume Flag */ |
| |
| #define | RFLAGS_VM 0x00020000 /* Virtual 8086 Mode */ |
| |
| #define | RFLAGS_AC 0x00040000 /* Alignment Check */ |
| |
| #define | RFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ |
| |
| #define | RFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ |
| |
| #define | RFLAGS_ID 0x00200000 /* CPUID Supported */ |
| |
| #define | DR7_DR0L 0x00000001 |
| |
| #define | DR7_DR0G 0x00000002 |
| |
| #define | DR7_DR1L 0x00000004 |
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| #define | DR7_DR1G 0x00000008 |
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| #define | DR7_DR2L 0x00000010 |
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| #define | DR7_DR2G 0x00000020 |
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| #define | DR7_DR3L 0x00000040 |
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| #define | DR7_DR3G 0x00000080 |
| |
| #define | MSR_EFER 0xC0000080 |
| |
| #define | EFER_SCE 0x0001 /* Syscall Enable */ |
| |
| #define | EFER_LME 0x0100 /* Long Mode Enable */ |
| |
| #define | EFER_LMA 0x0400 /* Long Mode Active */ |
| |
| #define | EFER_NXE 0x0800 /* Enable Execute Disable */ |
| |
| #define | EFER_SVME 0x1000 /* SVM Enable (AMD) */ |
| |
| #define | EFER_SLE 0x2000 /* Long Mode Segment Limit Enable (AMD) */ |
| |
| #define | EFER_FFXSR 0x4000 /* Fast FXSAVE/FXRSTOR (AMD) */ |
| |
| #define | EFER_TCE 0x8000 /* Translation Cache Extension (AMD) */ |
| |
| #define | MSR_STAR 0xC0000081 |
| |
| #define | MSR_LSTAR 0xC0000082 |
| |
| #define | MSR_CSTAR 0xC0000083 |
| |
| #define | MSR_SFMASK 0xC0000084 |
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1.9.6