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#define | CPUID_FLAG_APIC 0x100 |
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#define | IA32_APIC_BASE_MSR 0x1B |
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#define | IA32_APIC_BASE_MSR_BSP 0x100 |
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#define | IA32_APIC_BASE_MSR_ENABLE 0x800 |
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#define | LAPIC_ID 0x0020 /* CPU ID */ |
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#define | LAPIC_VERSION 0x0030 /* Version */ |
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#define | LAPIC_VERSION_LVTMASK 0x00FF0000 |
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#define | LAPIC_VERSION_LVTSHIFT 0x10 |
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#define | LAPIC_TPR 0x0080 /* Task Priority Register */ |
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#define | LAPIC_EOI 0x00B0 /* End of Interrupt */ |
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#define | LAPIC_SIV 0x00F0 /* Spurious Interrupt Vector */ |
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#define | LAPIC_SIV_ENABLE 0x100 |
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#define | LAPIC_ESR 0x0280 /* Error Status Register */ |
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#define | LAPIC_LVT_CMCI 0x02F0 /* LVT CMCI */ |
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#define | LAPIC_ICR_LO 0x0300 /* Interrupt Command Register */ |
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#define | LAPIC_ICR_HI 0x0310 /* Interrupt Command Register */ |
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#define | LAPIC_ICR_FIXED 0x0000 /* Delivery Mode */ |
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#define | LAPIC_ICR_NMI 0x0400 |
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#define | LAPIC_ICR_INIT 0x0500 |
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#define | LAPIC_ICR_STARTUP 0x0600 |
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#define | LAPIC_ICR_ASSERT 0x4000 |
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#define | LAPIC_ICR_TRIG 0x8000 |
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#define | LAPIC_ICR_SELF 0x00080000 /* Destination */ |
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#define | LAPIC_ICR_INCSELF 0x00080000 |
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#define | LAPIC_ICR_EXCSELF 0x000C0000 |
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#define | LAPIC_ICR_DELIVERY_PENDING 0x1000 /* Delivery Pending */ |
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#define | LAPIC_LVT_TIMER 0x0320 /* LVT Timer */ |
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#define | LAPIC_LVT_TIMER_ONESHOT 0x00000000 |
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#define | LAPIC_LVT_TIMER_PERIODIC 0x00020000 |
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#define | LAPIC_LVT_TIMER_TSCDEADLINE 0x00040000 |
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#define | LAPIC_LVT_THERMAL 0x0330 /* LVT Thermal Sensor */ |
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#define | LAPIC_LVT_PMCR 0x0340 /* LVT Performance Monitoring Counter */ |
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#define | LAPIC_LVT_LINT0 0x0350 /* LVT LINT0 */ |
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#define | LAPIC_LVT_LINT1 0x0360 /* LVT LINT1 */ |
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#define | LAPIC_LVT_ERROR 0x0370 /* LVT Error */ |
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#define | LAPIC_LVT_FLAG_MASKED 0x00010000 /* Masked */ |
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#define | LAPIC_LVT_FLAG_NMI 0x00000400 /* NMI */ |
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#define | LAPIC_LVT_FLAG_EXTINT 0x00000700 /* ExtINT */ |
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#define | LAPIC_TICR 0x0380 /* Timer Initial Count Register */ |
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#define | LAPIC_TCCR 0x0390 /* Timer Currnet Count Register */ |
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#define | LAPIC_TDCR 0x03E0 /* Time Divide Configuration Register */ |
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#define | LAPIC_TDCR_X1 0x000B /* Divide counts by 1 */ |
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