1
2 #include <stdbool.h>
3 #include <stdint.h>
4 #include <string.h>
5
6 #include <sys/kassert.h>
7 #include <sys/kdebug.h>
8 #include <sys/kmem.h>
9 #include <sys/semaphore.h>
10 #include <sys/pci.h>
11 #include <sys/irq.h>
12 #include <sys/mbuf.h>
13 #include <sys/nic.h>
14
15 #include <machine/pmap.h>
16
17 typedef struct E1000Device
18 {
19 uint32_t device;
20 const char *name;
21 uint32_t flags;
22 } E1000Device;
23
24 static E1000Device deviceList[] =
25 {
26 { 0x8086100e, "E1000", 0 }, // EERD is not supported
27 // { 0x80861209, "i82551", 0 }, // Doesn't seem to work on my qemu build
28 { 0, "", 0 },
29 };
30
31 void E1000_Configure(PCIDevice dev);
32
33 /*
34 * Hardware Structures
35 */
36
37 #define E1000_REG_CTRL 0x0000
38 #define E1000_REG_STATUS 0x0008
39 #define E1000_REG_EECD 0x0010
40 #define E1000_REG_EERD 0x0014
41 #define E1000_REG_ICR 0x00C0
42 #define E1000_REG_ICS 0x00C8
43 #define E1000_REG_IMS 0x00D0
44 #define E1000_REG_IMC 0x00D8
45 #define E1000_REG_RCTL 0x0100
46 #define E1000_REG_TCTL 0x0400
47
48 #define E1000_REG_RDBAL 0x2800
49 #define E1000_REG_RDBAH 0x2804
50 #define E1000_REG_RDLEN 0x2808
51 #define E1000_REG_RDH 0x2810
52 #define E1000_REG_RDT 0x2818
53 #define E1000_REG_RDTR 0x2820
54
55 #define E1000_REG_TDBAL 0x3800
56 #define E1000_REG_TDBAH 0x3804
57 #define E1000_REG_TDLEN 0x3808
58 #define E1000_REG_TDH 0x3810
59 #define E1000_REG_TDT 0x3818
60 #define E1000_REG_TIDV 0x3820
61 #define E1000_REG_TADV 0x382C
62
63 #define E1000_REG_MTABASE 0x5200
64
65 // EEPROM Offsets
66 #define NVM_MAC_ADDR 0x0000
67 #define NVM_DEVICE_ID 0x000D
68 #define NVM_VENDOR_ID 0x000E
69
70 // Control Flags
71 #define CTRL_SLU (1 << 6)
72
73 // Recieve Control Flags
74 #define RCTL_EN (1 << 1)
75 #define RCTL_SBP (1 << 2)
76 #define RCTL_UPE (1 << 3)
77 #define RCTL_MPE (1 << 4)
78 #define RCTL_LPE (1 << 5)
79 #define RCTL_BSIZE_1K (0x1 << 16)
80 #define RCTL_BSIZE_2K (0x0 << 16)
81 #define RCTL_BSIZE_4K ((1 << 25) | (0x3 << 16))
82 #define RCTL_BSIZE_8K ((1 << 25) | (0x2 << 16))
83 #define RCTL_BSIZE_16K ((1 << 25) | (0x1 << 16))
84
85 // Transmit Control Flags
86 #define TCTL_EN (1 << 1)
87 #define TCTL_PSP (1 << 3)
88
89 // Interrupt Control Register
90 #define ICR_TXDW (1 << 0)
91 #define ICR_LSC (1 << 2)
92 #define ICR_RXO (1 << 6)
93 #define ICR_RXT0 (1 << 7)
94
95 typedef struct PACKED E1000RXDesc {
96 volatile uint64_t addr; // Address
97 volatile uint16_t len; // Length
98 volatile uint16_t csum; // Checksum
99 volatile uint8_t status; // Status
100 volatile uint8_t errors; // Errors
101 volatile uint16_t special;
102 } E1000RXDesc;
103
104 #define RDESC_STATUS_EOP (1 << 1)
105 #define RDESC_STATUS_DD (1 << 0)
106
107 #define RDESC_ERROR_RDE (1 << 7) /* Receive Data Error */
108 #define RDESC_ERROR_CE (1 << 0) /* CRC Error */
109
110 typedef struct PACKED E1000TXDesc {
111 volatile uint64_t addr; // Address
112 volatile uint16_t len; // Length
113 volatile uint8_t cso; // Checksum Offset
114 volatile uint8_t cmd; // Command
115 volatile uint8_t status; // Status
116 volatile uint8_t css; // Checksum start
117 volatile uint16_t special;
118 } E1000TXDesc;
119
120 #define TDESC_CMD_RS (1 << 3) /* Report Status */
121 #define TDESC_CMD_IC (1 << 2) /* Insert Checksum */
122 #define TDESC_CMD_IFCS (1 << 1) /* Insert Ethernet FCS/CRC */
123 #define TDESC_CMD_EOP (1 << 0) /* End-of-Packet */
124
125 /*
126 * Driver Configuration and Structures
127 */
128
129 typedef struct E1000Dev {
130 NIC nic; // Must be first
131 PCIDevice dev;
132 IRQHandler irqHandle;
133 uint8_t *mmiobase;
134 E1000RXDesc *rxDesc;
135 E1000TXDesc *txDesc;
136 uint32_t rxTail;
137 uint32_t txTail;
138 Spinlock lock;
139 Semaphore ioSema;
140 } E1000Dev;
141
142 #define E1000_TX_QLEN 128
143 #define E1000_RX_QLEN 128
144
145 #define E1000_MAX_MTU 9000
146
147 // Memory Resources
148 static bool runOnce = false;
149 static Slab rxPool;
150 static Slab rxDescPool;
151 static Slab txDescPool;
152 DEFINE_SLAB(E1000RXDesc, &rxDescPool);
153 DEFINE_SLAB(E1000TXDesc, &txDescPool);
154
155 void *
RXPOOL_Alloc()156 RXPOOL_Alloc()
157 {
158 return Slab_Alloc(&rxPool);
159 }
160
161 void
RXPOOL_Free(void * buf)162 RXPOOL_Free(void *buf)
163 {
164 Slab_Free(&rxPool, buf);
165 }
166
167 void
E1000_Init(uint32_t bus,uint32_t slot,uint32_t func)168 E1000_Init(uint32_t bus, uint32_t slot, uint32_t func)
169 {
170 PCIDevice dev;
171
172 dev.bus = bus;
173 dev.slot = slot;
174 dev.func = func;
175 dev.vendor = PCI_GetVendorID(&dev);
176 dev.device = PCI_GetDeviceID(&dev);
177
178 uint32_t device = dev.vendor << 16 | dev.device;
179
180 int deviceIdx = 0;
181 while (deviceList[deviceIdx].device != 0x0) {
182 if (deviceList[deviceIdx].device == device) {
183 kprintf("E1000: Found %s\n", deviceList[deviceIdx].name);
184 // Configure and add disks
185 E1000_Configure(dev);
186 }
187
188 deviceIdx++;
189 }
190 }
191
192 static inline uint32_t
MMIO_Read32(E1000Dev * dev,uint64_t addr)193 MMIO_Read32(E1000Dev *dev, uint64_t addr)
194 {
195 return *(uint32_t volatile *)(dev->mmiobase + addr);
196 }
197
198 static inline void
MMIO_Write32(E1000Dev * dev,uint64_t addr,uint32_t val)199 MMIO_Write32(E1000Dev *dev, uint64_t addr, uint32_t val)
200 {
201 *(uint32_t *)(dev->mmiobase + addr) = val;
202 }
203
204 static uint16_t
E1000_EEPROM_Read(E1000Dev * dev,uint8_t addr)205 E1000_EEPROM_Read(E1000Dev *dev, uint8_t addr)
206 {
207 uint16_t val;
208
209 // Write Address
210 MMIO_Write32(dev, E1000_REG_EERD, ((uint32_t)addr << 8) | 1);
211
212 // Wait for ready bit
213 while (1) {
214 val = MMIO_Read32(dev, E1000_REG_EERD);
215 if (val & 0x10)
216 break;
217 }
218
219 kprintf("%08x\n", val);
220
221 return (uint16_t)((val >> 16) & 0x0000FFFF);
222 }
223
224 void
E1000_TXPoll(E1000Dev * dev)225 E1000_TXPoll(E1000Dev *dev)
226 {
227 // Free memory
228 kprintf("TXPOLL\n");
229 }
230
231 void
E1000_RXPoll(E1000Dev * dev)232 E1000_RXPoll(E1000Dev *dev)
233 {
234 while (dev->rxDesc[dev->rxTail].status & RDESC_STATUS_DD) {
235 //void *data = (void *)DMPA2VA(dev->rxDesc[dev->rxTail].addr);
236 //uint16_t len = dev->rxDesc[dev->rxTail].len;
237
238 // Look for packet fragments up to EOP set in status
239 if ((dev->rxDesc[dev->rxTail].status & RDESC_STATUS_EOP) &&
240 (dev->rxDesc[dev->rxTail].errors == 0)) {
241 // Process packet
242 /*
243 * XXX: Need to create a queue and copyout packets here, because
244 * I'm seeing multiple interrupts.
245 *
246 * kprintf("E1000: Int\n");
247 */
248 Semaphore_Release(&dev->ioSema);
249 }
250
251 if (dev->rxDesc[dev->rxTail].errors) {
252 kprintf("E1000: Error in RX Queue %x\n",
253 dev->rxDesc[dev->rxTail].errors);
254 dev->rxDesc[dev->rxTail].status = 0;
255 dev->rxDesc[dev->rxTail].errors = 0;
256 MMIO_Write32(dev, E1000_REG_RDT, dev->rxTail);
257 dev->rxTail = (dev->rxTail + 1) % E1000_RX_QLEN;
258 }
259
260 /*
261 dev->rxDesc[dev->rxTail].status = 0;
262 dev->rxDesc[dev->rxTail].errors = 0;
263 // XXX: Should write this only once
264 MMIO_Write32(dev, E1000_REG_RDT, dev->rxTail);
265 dev->rxTail = (dev->rxTail + 1) % E1000_RX_QLEN;
266 */
267 }
268 }
269
270 void
E1000_Interrupt(void * arg)271 E1000_Interrupt(void *arg)
272 {
273 E1000Dev *dev = (E1000Dev *)arg;
274
275 kprintf("E1000 (%d:%d) Interrupt\n",
276 dev->dev.bus, dev->dev.slot);
277
278 uint32_t cause = MMIO_Read32(dev, E1000_REG_ICR);
279
280 // Link Status
281 if (cause & ICR_LSC) {
282 cause &= ~ICR_LSC;
283 MMIO_Write32(dev, E1000_REG_CTRL, MMIO_Read32(dev, E1000_REG_CTRL) | CTRL_SLU);
284 }
285
286 // Transmit Queue Empty
287 if (cause & 3) {
288 cause &= ~3;
289 E1000_TXPoll(dev);
290 }
291
292 // Receive Overrun
293 if (cause & ICR_RXO) {
294 cause &= ~ICR_RXO;
295 kprintf("underrun %u %u\n", MMIO_Read32(dev, E1000_REG_RDH), dev->rxTail);
296
297 E1000_RXPoll(dev);
298 }
299
300 // Receive Timer
301 if (cause & ICR_RXT0) {
302 cause &= ~ICR_RXT0;
303 E1000_RXPoll(dev);
304 }
305
306 if (cause != 0) {
307 kprintf("E1000: Unhandled cause %08x\n", cause);
308 }
309
310 MMIO_Read32(dev, E1000_REG_ICR);
311 }
312
313 /*
314 * Read packets from NIC
315 */
316 int
E1000_Dequeue(NIC * nic,MBuf * mbuf,NICCB cb,void * arg)317 E1000_Dequeue(NIC *nic, MBuf *mbuf, NICCB cb, void *arg)
318 {
319 E1000Dev *dev = (E1000Dev *)nic;
320
321 retry:
322 Semaphore_Acquire(&dev->ioSema);
323
324 Spinlock_Lock(&dev->lock);
325 if ((dev->rxDesc[dev->rxTail].status & RDESC_STATUS_EOP) &&
326 (dev->rxDesc[dev->rxTail].errors == 0)) {
327 void *data = (void *)DMPA2VA(dev->rxDesc[dev->rxTail].addr);
328 uint16_t len = dev->rxDesc[dev->rxTail].len;
329
330 //Debug_PrintHex(data, len, 0, len);
331 // Use CB instead
332 memcpy((void *)mbuf->vaddr, data, len);
333
334 dev->rxDesc[dev->rxTail].status = 0;
335 dev->rxDesc[dev->rxTail].errors = 0;
336 // XXX: Should write this only once
337 MMIO_Write32(dev, E1000_REG_RDT, dev->rxTail);
338 dev->rxTail = (dev->rxTail + 1) % E1000_RX_QLEN;
339 } else {
340 /*
341 * XXX: Need to remove this once I do the copyout inside the interrupt
342 * handler.
343 */
344 /*kprintf("Packet not ready %d %x %x\n",
345 dev->rxTail,
346 dev->rxDesc[dev->rxTail].status,
347 dev->rxDesc[dev->rxTail].errors);*/
348 Spinlock_Unlock(&dev->lock);
349 goto retry;
350 }
351 Spinlock_Unlock(&dev->lock);
352
353 return 0;
354 }
355
356 /*
357 * Transmit packets
358 */
359 int
E1000_Enqueue(NIC * nic,MBuf * mbuf,NICCB cb,void * arg)360 E1000_Enqueue(NIC *nic, MBuf *mbuf, NICCB cb, void *arg)
361 {
362 E1000Dev *dev = (E1000Dev *)nic;
363 void *data = (void *)DMPA2VA(dev->txDesc[dev->txTail].addr);
364
365 // Copy data
366 memcpy(data, (void *)mbuf->vaddr, mbuf->len);
367 dev->txDesc[dev->txTail].len = mbuf->len;
368
369 dev->txDesc[dev->txTail].cmd = TDESC_CMD_EOP | TDESC_CMD_IFCS | TDESC_CMD_RS;
370 MMIO_Write32(dev, E1000_REG_TDT, dev->txTail);
371 dev->txTail = (dev->txTail + 1) % E1000_TX_QLEN;
372
373 // Wait for transmit to complete
374
375 return 0;
376 }
377
378 void
E1000_RXInit(E1000Dev * dev)379 E1000_RXInit(E1000Dev *dev)
380 {
381 int i;
382
383 // Zero out Multicast Table Array
384 for (i = 0; i < 128; i++) {
385 MMIO_Write32(dev, E1000_REG_MTABASE + (i * 4), 0);
386 }
387
388 dev->rxDesc = (E1000RXDesc *)E1000RXDesc_Alloc();
389 for (i = 0; i < E1000_RX_QLEN; i++) {
390 dev->rxDesc[i].addr = VA2PA((uintptr_t)PAlloc_AllocPage()); // LOOKUP IN PMAP
391 dev->rxDesc[i].status = 0;
392 }
393
394 // Setup base and length of recieve descriptors
395 uintptr_t base = VA2PA((uintptr_t)dev->rxDesc);
396 MMIO_Write32(dev, E1000_REG_RDBAH, (uint32_t)(base >> 32));
397 MMIO_Write32(dev, E1000_REG_RDBAL, (uint32_t)(base & 0xFFFFFFFF));
398 MMIO_Write32(dev, E1000_REG_RDLEN, E1000_RX_QLEN * 16);
399
400 MMIO_Write32(dev, E1000_REG_RDH, 0);
401 MMIO_Write32(dev, E1000_REG_RDT, E1000_RX_QLEN);
402 dev->rxTail = 0;
403
404 MMIO_Write32(dev, E1000_REG_RCTL,
405 (RCTL_EN | RCTL_UPE | RCTL_MPE | RCTL_BSIZE_4K));
406 }
407
408 void
E1000_TXInit(E1000Dev * dev)409 E1000_TXInit(E1000Dev *dev)
410 {
411 int i;
412
413 dev->txDesc = (E1000TXDesc *)E1000RXDesc_Alloc();
414 for (i = 0; i < E1000_TX_QLEN; i++) {
415 dev->txDesc[i].addr = VA2PA((uintptr_t)PAlloc_AllocPage()); // LOOKUP IN PMAP
416 dev->txDesc[i].cmd = 0;
417 }
418
419 // Setup base and length of recieve descriptors
420 uintptr_t base = VA2PA((uintptr_t)dev->txDesc);
421 MMIO_Write32(dev, E1000_REG_TDBAH, (uint32_t)(base >> 32));
422 MMIO_Write32(dev, E1000_REG_TDBAL, (uint32_t)(base & 0xFFFFFFFF));
423 MMIO_Write32(dev, E1000_REG_TDLEN, E1000_TX_QLEN * 16);
424
425 MMIO_Write32(dev, E1000_REG_TDH, 0);
426 MMIO_Write32(dev, E1000_REG_TDT, 0);
427 dev->txTail = 0;
428
429 // Interrupt Delay Timers
430 MMIO_Write32(dev, E1000_REG_TIDV, 1);
431 MMIO_Write32(dev, E1000_REG_TADV, 1);
432
433 MMIO_Write32(dev, E1000_REG_TCTL, TCTL_EN | TCTL_PSP);
434 }
435
436 void
E1000_Configure(PCIDevice dev)437 E1000_Configure(PCIDevice dev)
438 {
439 E1000Dev *ethDev = (E1000Dev *)PAlloc_AllocPage();
440 PCI_Configure(&dev);
441
442 // Ensure that the NIC structure is the first thing inside E1000Dev
443 ASSERT((void *)ethDev == (void *)ðDev->nic);
444
445 if (!runOnce) {
446 runOnce = true;
447
448 //E1000_MAX_MTU + 14 + 4, 4096);
449 Slab_Init(&rxPool, "E1000 RX Pool", 4096, 4096);
450 Slab_Init(&rxDescPool, "E1000 RX Descriptors", E1000_RX_QLEN*sizeof(E1000RXDesc), 16);
451 Slab_Init(&txDescPool, "E1000 TX Descriptors", E1000_TX_QLEN*sizeof(E1000TXDesc), 16);
452 }
453
454 // Copy PCIDevice structure
455 memcpy(ðDev->dev, &dev, sizeof(dev));
456
457 // MMIO
458 int bar;
459 for (bar = 0; bar < PCI_MAX_BARS; bar++) {
460 if (dev.bars[bar].size == 0)
461 continue;
462
463 kprintf("E1000: BAR%d base=%08x size=%08x %s\n",
464 bar, dev.bars[bar].base, dev.bars[bar].size,
465 dev.bars[bar].type == PCIBAR_TYPE_IO ? "IO" : "Mem");
466 }
467
468 ethDev->mmiobase = (uint8_t *)DMPA2VA(dev.bars[0].base);
469
470 // Enable Link
471 MMIO_Write32(ethDev, E1000_REG_CTRL, MMIO_Read32(ethDev, E1000_REG_CTRL) | CTRL_SLU);
472
473 // Register IRQs
474 kprintf("E1000: IRQ %d\n", dev.irq);
475 ethDev->irqHandle.irq = dev.irq;
476 ethDev->irqHandle.cb = &E1000_Interrupt;
477 ethDev->irqHandle.arg = ethDev;
478 IRQ_Register(dev.irq, ðDev->irqHandle);
479
480 kprintf("E1000: MAC XX:XX:XX:XX:XX:XX\n");
481 for (int i = 0; i < 3; i++) {
482 E1000_EEPROM_Read(ethDev, NVM_MAC_ADDR + 2*i);
483 }
484
485 // Device lock
486 Spinlock_Init(ðDev->lock, "E1000 Spinlock", SPINLOCK_TYPE_NORMAL);
487
488 // IO Semaphore
489 Semaphore_Init(ðDev->ioSema, 0, "E1000 Semaphore");
490 ethDev->nic.tx = &E1000_Enqueue;
491 ethDev->nic.rx = &E1000_Dequeue;
492
493 // Enable interrupts
494 //MMIO_Write32(ethDev, E1000_REG_IMC, ~0);
495 MMIO_Write32(ethDev, E1000_REG_IMS, 0x1F6DC); //ICR_TXDW | ICR_RXO | ICR_RXT0);
496 MMIO_Read32(ethDev, E1000_REG_ICR); // Clear pending interrupts
497
498 E1000_RXInit(ethDev);
499 E1000_TXInit(ethDev);
500
501 ethDev->nic.handle = ethDev;
502 // XXX: Fill in callbacks
503 NIC_AddNIC(ðDev->nic);
504 }
505
506