1 /* 2 * Copyright (c) 2013-2018 Ali Mashtizadeh 3 * All rights reserved. 4 */ 5 6 #ifndef __AMD64_H__ 7 #define __AMD64_H__ 8 9 #include <sys/cdefs.h> 10 11 /* 12 * Page Tables 13 */ 14 15 #define PGNUMMASK 0xFFFFFFFFFFFFF000ULL 16 17 #define PGIDXSHIFT 9 18 #define PGIDXMASK (512 - 1) 19 20 #define PGSHIFT 12 21 #define PGSIZE (1 << PGSHIFT) 22 #define PGMASK (PGSIZE - 1) 23 24 #define LARGE_PGSHIFT 21 25 #define LARGE_PGSIZE (1 << LARGE_PGSHIFT) 26 #define LARGE_PGMASK (LARGE_PGSIZE - 1) 27 28 #define HUGE_PGSHIFT 30 29 #define HUGE_PGSIZE (1 << HUGE_PGSHIFT) 30 #define HUGE_PGMASK (HUGE_PGSIZE - 1) 31 32 #define ROUNDUP_PGSIZE(x) (((x) + LARGE_PGSIZE - 1) & ~LARGE_PGMASK) 33 #define ROUNDDOWN_PGSIZE(x) ((x) & ~LARGE_PGMASK) 34 35 #define PTE_P 0x0001 /* Present */ 36 #define PTE_W 0x0002 /* Writeable */ 37 #define PTE_U 0x0004 /* User */ 38 #define PTE_PWT 0x0008 /* Write Through */ 39 #define PTE_PCD 0x0010 /* Cache Disable */ 40 #define PTE_A 0x0020 /* Accessed */ 41 #define PTE_D 0x0040 /* Dirty */ 42 #define PTE_PS 0x0080 /* Page Size */ 43 #define PTE_G 0x0100 /* Global */ 44 #define PTE_OS1 0x0200 /* Available */ 45 #define PTE_OS2 0x0400 /* Available */ 46 #define PTE_OS3 0x0800 /* Available */ 47 #define PTE_PAT 0x1000 /* Page Attribute Table */ 48 #define PTE_NX 0x8000000000000000ULL /* No Execute */ 49 50 #define PAGETABLE_ENTRIES 512 51 52 typedef uint64_t PageEntry; 53 54 typedef struct PageTable { 55 PageEntry entries[PAGETABLE_ENTRIES]; 56 } PageTable; 57 58 /* 59 * Global Descriptor Table 60 */ 61 62 typedef struct PACKED PseudoDescriptor { 63 uint16_t lim; 64 uint64_t off; 65 } PseudoDescriptor; 66 67 #define SEG_G 68 #define SEG_DB 69 #define SEG_L 70 #define SEG_P 71 #define SEG_DPL_SHIFT 45 72 #define SEG_S 73 74 #define SEG_CS (0xE << 40) 75 #define SEG_DS (0x2 << 40) 76 77 #define SEG_TSA (0x9 << 40) 78 #define SEG_TSB (0xB << 40) 79 80 #define SEL_KCS 0x08 81 #define SEL_KDS 0x10 82 #define SEL_TSS 0x20 83 #define SEL_UCS 0x30 84 #define SEL_UDS 0x38 85 86 typedef uint64_t SegmentDescriptor; 87 88 /* 89 * Interrupt Descriptor Table 90 */ 91 92 typedef struct PACKED InteruptGate64 { 93 uint16_t pc_low; 94 uint16_t cs; 95 uint8_t ist; 96 uint8_t type; 97 uint16_t pc_mid; 98 uint32_t pc_high; 99 uint32_t _unused1; 100 } InteruptGate64; 101 102 /* 103 * Task State Segment 104 */ 105 106 typedef struct PACKED TaskStateSegment64 { 107 uint32_t _unused0; 108 uint64_t rsp0; 109 uint64_t rsp1; 110 uint64_t rsp2; 111 uint64_t _unused1; 112 uint64_t ist1; 113 uint64_t ist2; 114 uint64_t ist3; 115 uint64_t ist4; 116 uint64_t ist5; 117 uint64_t ist6; 118 uint64_t ist7; 119 uint32_t _unused2; 120 uint32_t _unused3; 121 uint16_t _unused4; 122 uint16_t iomap_offset; 123 } TaskStateSegment64; 124 125 /* 126 * XSAVE Area 127 */ 128 129 typedef struct XSAVEArea 130 { 131 uint16_t fcw; 132 uint16_t fsw; 133 uint8_t ftw; 134 uint8_t _rsvd0; 135 uint16_t fop; 136 uint64_t fpuip; 137 uint64_t fpudp; 138 uint32_t mxcsr; 139 uint32_t mxcsr_mask; 140 uint64_t mmx[16]; // ST(n)/MMn (80-bits padded) 141 uint64_t xmm[32]; // XMM0-XMM15 142 } XSAVEArea; 143 144 /* 145 * Control Registers 146 */ 147 148 #define CR0_PE 0x00000001 /* Protection Enabled */ 149 #define CR0_MP 0x00000002 /* Monitor Coprocessor */ 150 #define CR0_EM 0x00000004 /* Emulation */ 151 #define CR0_TS 0x00000008 /* Task Switched */ 152 #define CR0_ET 0x00000010 /* Extension Type */ 153 #define CR0_NE 0x00000020 /* Numeric Error */ 154 #define CR0_WP 0x00010000 /* Write Protect */ 155 #define CR0_AM 0x00040000 /* Alignment Mask */ 156 #define CR0_NW 0x20000000 /* Not Writethrough */ 157 #define CR0_CD 0x40000000 /* Cache Disable */ 158 #define CR0_PG 0x80000000 /* Paging */ 159 160 #define CR4_VME 0x00000001 /* Virtual 8086 Mode Enable */ 161 #define CR4_PVI 0x00000002 /* Protected-Mode Virtual Interupts */ 162 #define CR4_TSD 0x00000004 /* Time Stamp Diable */ 163 #define CR4_DE 0x00000008 /* Debugging Extensions */ 164 #define CR4_PSE 0x00000010 /* Page Size Extensions */ 165 #define CR4_PAE 0x00000020 /* Physical Address Extension */ 166 #define CR4_MCE 0x00000040 /* Machine Check Enable */ 167 #define CR4_PGE 0x00000080 /* Page Global Enable */ 168 #define CR4_PCE 0x00000100 /* Performance Monitoring Counter Enable */ 169 #define CR4_OSFXSR 0x00000200 /* OS FXSAVE/FXRSTOR Support */ 170 #define CR4_OSXMMEXCPT 0x00000400 /* OS Unmasked Exception Support */ 171 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS read/write Instructions */ 172 #define CR4_OSXSAVE 0x00040000 /* XSAVE and Processor Extended States Enable */ 173 174 #define RFLAGS_CF 0x00000001 /* Carry Flag */ 175 #define RFLAGS_PF 0x00000004 /* Parity Flag */ 176 #define RFLAGS_AF 0x00000010 /* Adjust Flag */ 177 #define RFLAGS_ZF 0x00000040 /* Zero Flag */ 178 #define RFLAGS_SF 0x00000080 /* Sign Flag */ 179 #define RFLAGS_TF 0x00000100 /* Trap Flag */ 180 #define RFLAGS_IF 0x00000200 /* Interrupt Enable Flag */ 181 #define RFLAGS_DF 0x00000400 /* Direction Flag */ 182 #define RFLAGS_OF 0x00000800 /* Overflow Flag */ 183 // IOPL (bits 12-13) 184 #define RFLAGS_NT 0x00004000 /* Nested Task Flag */ 185 #define RFLAGS_RF 0x00010000 /* Resume Flag */ 186 #define RFLAGS_VM 0x00020000 /* Virtual 8086 Mode */ 187 #define RFLAGS_AC 0x00040000 /* Alignment Check */ 188 #define RFLAGS_VIF 0x00080000 /* Virtual Interrupt Flag */ 189 #define RFLAGS_VIP 0x00100000 /* Virtual Interrupt Pending */ 190 #define RFLAGS_ID 0x00200000 /* CPUID Supported */ 191 192 /* 193 * Debug Registers 194 */ 195 196 #define DR7_DR0L 0x00000001 197 #define DR7_DR0G 0x00000002 198 #define DR7_DR1L 0x00000004 199 #define DR7_DR1G 0x00000008 200 #define DR7_DR2L 0x00000010 201 #define DR7_DR2G 0x00000020 202 #define DR7_DR3L 0x00000040 203 #define DR7_DR3G 0x00000080 204 205 /* 206 * MSRs 207 */ 208 209 #define MSR_EFER 0xC0000080 210 211 #define EFER_SCE 0x0001 /* Syscall Enable */ 212 #define EFER_LME 0x0100 /* Long Mode Enable */ 213 #define EFER_LMA 0x0400 /* Long Mode Active */ 214 #define EFER_NXE 0x0800 /* Enable Execute Disable */ 215 #define EFER_SVME 0x1000 /* SVM Enable (AMD) */ 216 #define EFER_SLE 0x2000 /* Long Mode Segment Limit Enable (AMD) */ 217 #define EFER_FFXSR 0x4000 /* Fast FXSAVE/FXRSTOR (AMD) */ 218 #define EFER_TCE 0x8000 /* Translation Cache Extension (AMD) */ 219 220 // SYSCALL/SYSRET 221 #define MSR_STAR 0xC0000081 222 #define MSR_LSTAR 0xC0000082 223 #define MSR_CSTAR 0xC0000083 224 #define MSR_SFMASK 0xC0000084 225 226 #include "amd64op.h" 227 228 #endif /* __AMD64_H__ */ 229 230