2#define PCI_OFFSET_VENDORID 0x00
3#define PCI_OFFSET_DEVICEID 0x02
4#define PCI_OFFSET_COMMAND 0x04
5#define PCI_OFFSET_STATUS 0x06
6#define PCI_OFFSET_REVISIONID 0x08
7#define PCI_OFFSET_PROGIF 0x09
8#define PCI_OFFSET_SUBCLASS 0x0A
9#define PCI_OFFSET_CLASS 0x0B
10#define PCI_OFFSET_CACHELINE 0x0C
11#define PCI_OFFSET_LATENCYTMR 0x0D
12#define PCI_OFFSET_HEADERTYPE 0x0E
13#define PCI_OFFSET_BIST 0x0F
15#define PCI_OFFSET_BARFIRST 0x10
16#define PCI_OFFSET_BARLAST 0x24
18#define PCI_OFFSET_IRQLINE 0x3C
20#define PCI_COMMAND_IOENABLE 0x0001
21#define PCI_COMMAND_MEMENABLE 0x0002
22#define PCI_COMMAND_BUSMASTER 0x0004
26#define PCI_CLASS_STORAGE 0x01
27#define PCI_CLASS_NETWORK 0x02
28#define PCI_CLASS_GRAPHICS 0x03
29#define PCI_CLASS_BRIDGE 0x06
30#define PCI_CLASS_BUS 0x0C
32#define PCI_SCLASS_STORAGE_IDE 0x01
33#define PCI_SCLASS_STORAGE_SATA 0x06
35#define PCI_SCLASS_BRIDGE_HOST 0x00
36#define PCI_SCLASS_BRIDGE_ISA 0x01
37#define PCI_SCLASS_BRIDGE_PCI 0x04
38#define PCI_SCLASS_BRIDGE_MISC 0x80
40#define PCI_SCLASS_BUS_FW 0x00
41#define PCI_SCLASS_BUS_USB 0x03
42#define PCI_SCLASS_BUS_SMBUS 0x05
44#define PCIBAR_TYPE_NULL 0
45#define PCIBAR_TYPE_IO 1
46#define PCIBAR_TYPE_MEM 2
void PCI_CfgWrite32(PCIDevice *dev, uint32_t reg, uint32_t data)
uint8_t PCI_GetHeaderType(PCIDevice *dev)
void PCI_CfgWrite8(PCIDevice *dev, uint32_t reg, uint8_t data)
uint16_t PCI_GetVendorID(PCIDevice *dev)
uint8_t PCI_GetBaseClass(PCIDevice *dev)
uint16_t PCI_GetDeviceID(PCIDevice *dev)
void PCI_CfgWrite16(PCIDevice *dev, uint32_t reg, uint16_t data)
PCIBAR bars[PCI_MAX_BARS]
uint32_t PCI_CfgRead32(PCIDevice *dev, uint32_t reg)
void PCI_Configure(PCIDevice *dev)
uint16_t PCI_CfgRead16(PCIDevice *dev, uint32_t reg)
uint8_t PCI_CfgRead8(PCIDevice *dev, uint32_t reg)
uint8_t PCI_GetSubClass(PCIDevice *dev)